1. Field of the Invention
This invention relates to the field of computer systems. More specifically this invention relates to write cycles performed in a computer system.
2. Related Art
A computer system typically comprises a processor, a bus, memory, and other peripheral devices. The processor is responsible for executing instructions using the data in the computer system. The bus serves as a communication pathway between the processor and the other devices for transferring information between one another. The memory subsystem stores data and instructions for the processor and other resources of the computer system. A memory controller controls access by the processor and other devices to the memory devices in the memory subsystem.
In many prior art systems, the overall system performance is linked to the performance of the memory subsystem. To realize the performance potential of many prior art processors, a prior art system must use relatively fast memory devices. However, because of the cost of fast memory devices, some prior art systems are not able to use only fast memory devices, such that performance does not reach its potential.
To resolve the cost-performance tradeoff, prior art systems partition system functions by using a combination of fast and slow memory devices. If the most frequently used functions are stored on the fast memory device, all the other functions are stored on the slow memory device. One prior art memory configuration uses Dynamic Random Access Memory (DRAM) devices which are slow but cheap for slow memory, and Static Random Access Memory (SRAM) devices which are more expensive, yet faster, for fast memory.
Prior art computer systems typically include a memory controller for controlling access to the memory devices. Although various types of memory may be installed in the computer system, the memory controller must be configured to correctly access both fast and slow memory without unnecessarily wasting processor resources.
The peripherals in a computer system communicate to the processor via a host or system bus. The bus cycle for the processor is the period of time taken to send an address on the system bus from the processor to memory and to transfer data between the memory and the processor. The bus cycle is typically measured in clock cycles. For example, it can take the processor three clock cycles to send an address to memory and two clock cycles to receive data from memory. The number of clocks for each operation determines the bus cycle length. The functional operation of the bus and the bus cycle length used (herein referred to as cycle length) when the processor is accessing other peripherals in the computer system depends on the parameters established for the particular bus and the bus controller used by it to control access to the bus. Fast memory devices coupled to the memory controller can communicate to the processor at shorter bus cycle lengths while slow memory devices require longer cycle lengths.
FIG. 1 illustrates a prior art system having a processor 12 for executing data and instructions. Processor 12 is coupled to local bus 10. Local bus 10 provides a communication pathway between processor 12 and other peripherals of the computer system. Processor 12 also transfers data to the memory devices.
Bus control unit (BCU) 14 manages communications between peripherals 20 on the system bus 22 and processor 12 via the local bus 10. Memory controller 16 is shown coupled to system bus 22. Memory controller 16 manages communications between processor 12 and memory device 18. Memory device 18 is coupled to memory controller 16 and it is used to store data and information in the computer system.
A write cycle to memory typically begins with processor 12 driving an address on local bus 10. A write signal is sent to memory device 18 via BCU 14 and memory controller 16. BCU 14 manages the communication of the address signals from processor 12 on the local bus 10 and system bus 22. The memory controller 16 controls the access to memory device 18 according to the memory destination specified in the address generated by processor 12. The time taken to write to the memory location specified by the address generated by processor 12 is known as a write cycle.
Many prior art processors in order to perform a write operation to both slow and fast memory devices insert wait states in their write cycles. Wait states are additional bus cycles which extend the time (number of clock cycles) required to perform a write cycle operation. Wait states are inserted in order to allow enough time to complete the write cycle.
During wait states, the processor is typically idle. This wastes the processor resources and directly affects the efficiency of the prior art computer system. Since the processor could be performing other instructions instead of being in an idle state waiting for a write cycle to complete, the addition of extra clocks to complete a write cycle impedes the processor's potential performance, thereby affecting the performance of a computer system.
The extended time required to perform writes to slow memory devices with inserted wait states has proved unacceptable to many system designers. To improve prior art system performance and still accommodate slow memory devices, several techniques are being used. One such technique is the pipelining of bus cycles. Pipelining is a processor instruction fetches, decoding, and execution overlapping technique to maximize processor throughput and bus utilization. Pipelining allows the overlapping of bus cycles to decrease the amount of time for the memory to respond to processor requests. Pipelining also decreases the address access time by one or more clock cycles for the processor. So for example, if a non-pipelined write cycle to memory has three wait states, pipelining such a write cycle will decrease the number of wait states to two.
FIG. 2 illustrates an example of a pipelined write cycle of the prior art system. Referring to FIG. 2, the clocks are labelled 1-6 and the signals are labelled with a "#" to indicate that a signal is low when asserted (i.e., active low). In clock 1, processor 12 initiates a write cycle by asserting address strobe (ADS#) signal 200 and driving an address on the address bus. In clock 3, the next address (NA# 220) signal is asserted. Because the first write cycle (cycle 1) has not yet completed, the next address is not driven until clock 5 when address strobe (ADS#) signal 200 is asserted to start the next write cycle (cycle 2). The memory controller of the prior art system waits until clock 3 to assert next address (NA#) signal 220 because it assumes the first cycle (cycle 1) is going to slow memory (even if the cycle is really to fast memory) thereby slowing the computer system down.
Although pipelining helps prior art processors increase their performance, the performance is less than the potential performance of some advanced processors. The higher clock frequencies and fast memory cycle times supported by these advanced processors often force the insertion of unnecessary wait states during write cycles to fast memory devices in the prior art systems. The unnecessary wait states are included because the decision to insert wait states is made before any determination is made as to whether the write cycle is directed to a fast or slow memory device. Thus, prior art systems include wait states in write cycles to both fast and slow memories. It is desirable to have a computer system that includes wait states when they are needed and to not include wait states when they are not required.
The present invention provides for performing write operations in a computer system to both fast and slow memories. The present invention causes wait states to be inserted in the write cycles in order to compensate for slow memory devices and not for fast memory devices. Thus, the present invention uses variable length write cycles when performing write operations.